Three dimensional metal-oxide-semiconductor field-effect transistors (“MOSFETs”), often referred to as MultiGate FET (“MUGFETs”), “finFETs,” or “TriGate FETs,” are expected to be adopted in complementary metal-oxide-semiconductor (“CMOS”) device fabrication at the 32 nm technology node in order to alleviate issues with short channel effects. Manufacture of a three dimensional MOSFET requires masked etching of silicon to create a raised cuboid of silicon referred to in the art as a “fin” that serves as the body of the transistor. In the manufacture of the three dimensional transistor, control of the fin length, depth, and height are key process control factors. The typical height of the fin is between about 50 nm and about 100 nm. The means of controlling fin height depends upon the silicon wafer. The fin length and depth are controlled in device processing by photolithography and etching. After formation of the fin, the transistor gate, source, and drain are then formed around the silicon fin.
Silicon on insulator (“SOI”) wafers have been the focus of research on the development of three dimensional transistors since the buried oxide layer in a SOI wafer is a natural etch stop during plasma etching of the fin due to etch rate selectivity between silicon and silicon dioxide. The SOI film thickness, therefore, determines the height of the film and the height uniformity. FIG. 1 depicts a three dimensional MOSFET 1 fabricated on an SOI wafer substrate 3 comprising an oxide layer 5. The silicon fin 7 is a raised, free standing rectangle of silicon that is contacted by source 9 and drain 11 on its ends, and has a gate dielectric and electrode surrounding it on three sides. The transistor gate length is determined by the gate dimension 13. The transistor gate width is determined by the height of the fin.
The SOI wafer, however, does not contribute to improved device performance of the three dimensional transistor. The SOI wafer may degrade thermal conductivity compared to polished bulk wafers or epitaxial wafers. Moreover, the use of SOI wafer is disadvantageous from a cost perspective compared to fabricating a three-dimensional transistor on a non-SOI bulk wafer. See H. Wong, “Beyond The Conventional Transistor, IBM J. Res. & Dev., VOL 46 NO 2/3 March/May 2002; B. Doyle et al., “Tri-Gate Fully Depleted CMOS Transistors: Fabrication, Design and Layout”, VLSI Symposium 2003; and J. Kavalieros, et al, “Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering”, VLSI Symposium 2006.
FIG. 2 is a cross section diagram of a three dimensional transistor 15 fabricated on a bulk silicon substrate 17 based on work reported in T. Park et al., “Fabrication of Body-Tied FinFETs Using Bulk Wafers,” VLSI Symposium 2003 and K. Okano, et al., “Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with Sub-10 nm Fin Width and 20 nm Gate Length,” IEDM 2005. Trenches between about 200 nm and about 300 nm deep are etched into the silicon, forming a fin 19 having a total fin height of between about 200 nm and about 300 nm. Then, a SiN layer 21 and a SiO2 layer 23 are added to define the fin active height which is on the order of one-third to one-half the total fin height. The gate dielectric 25 and electrode surround it on three sides. The top portion of the fin is tailored to the desired length and depth. For the bulk wafer, the total fin height is determined by the etch process, while the active transistor fin height is determined by the total fin height minus the SiN layer and subsequent trimming of the top of the fin. Bulk wafers present a transistor processing challenge since they lack the built-in oxide etch stop available on the SOT wafer.
Therefore, manufacture of three dimensional transistors in bulk wafers may be improved by adding a layer near the surface that can provide endpoint detection during plasma etching of the fin, thereby determining the fin height. This may be achieved during device fabrication by ion implantation of an implantable species at a concentration capable of creating a change in etch rate or providing an endpoint detection. Ion implant enables precise depth control over the entire wafer surface area, and offers precise dose control and flexibility in the selection of the chemical species. A negative effect occurs, however, when the implant species travels through the device region and disorders the silicon lattice. Following ion implant, thermal annealing is required to activate the implant species into silicon lattice sites and to eliminate or reduce residual damage caused by the ion implant. Another potential disadvantage of ion implantation is the broad depth distribution of the ion implanted species, which may affect the ability of the subsequent etching process to define fins of precise heights.
U.S. Pat. No. 6,642,090 discloses two ion implant methods for fin height control in bulk substrates. In one method, ion implant damage evolves a differential etch rate between the damaged trench area and the undamaged fin. In another method, a marker layer is implanted using an impurity that can be detected during plasma etching.